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Freescale Semiconductor /MK20D10 /SPI1 /CTAR1

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Interpret as CTAR1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BR0DT0ASC0CSSCK0 (00)PBR0 (00)PDT0 (00)PASC 0 (00)PCSSCK 0 (0)LSBFE 0 (0)CPHA 0 (0)CPOL 0FMSZ0 (0)DBR

DBR=0, PDT=00, LSBFE=0, CPHA=0, PCSSCK=00, PBR=00, PASC=00, CPOL=0

Description

DSPI Clock and Transfer Attributes Register (In Master Mode)

Fields

BR

Baud Rate Scaler
DT

Delay After Transfer Scaler
ASC

After SCK Delay Scaler
CSSCK

PCS to SCK Delay Scaler
PBR

Baud Rate Prescaler

0 (00): Baud Rate Prescaler value is 2.

1 (01): Baud Rate Prescaler value is 3.

2 (10): Baud Rate Prescaler value is 5.

3 (11): Baud Rate Prescaler value is 7.
PDT

Delay after Transfer Prescaler

0 (00): Delay after Transfer Prescaler value is 1.

1 (01): Delay after Transfer Prescaler value is 3.

2 (10): Delay after Transfer Prescaler value is 5.

3 (11): Delay after Transfer Prescaler value is 7.
PASC

After SCK Delay Prescaler

0 (00): Delay after Transfer Prescaler value is 1.

1 (01): Delay after Transfer Prescaler value is 3.

2 (10): Delay after Transfer Prescaler value is 5.

3 (11): Delay after Transfer Prescaler value is 7.
PCSSCK

PCS to SCK Delay Prescaler

0 (00): PCS to SCK Prescaler value is 1.

1 (01): PCS to SCK Prescaler value is 3.

2 (10): PCS to SCK Prescaler value is 5.

3 (11): PCS to SCK Prescaler value is 7.
LSBFE

LSB First

0 (0): Data is transferred MSB first.

1 (1): Data is transferred LSB first.
CPHA

Clock Phase

0 (0): Data is captured on the leading edge of SCK and changed on the following edge.

1 (1): Data is changed on the leading edge of SCK and captured on the following edge.
CPOL

Clock Polarity

0 (0): The inactive state value of SCK is low.

1 (1): The inactive state value of SCK is high.
FMSZ

Frame Size
DBR

Double Baud Rate

0 (0): The baud rate is computed normally with a 50/50 duty cycle.

1 (1): The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data